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motorola, inc., 1998 AN1759 order this document by AN1759/d AN1759 add a non-volatile clock to the mc68hc705j1a by mark glenewinkel field applications engineering consumer systems group austin, texas introduction many embedded systems require the measurement of time. this can be accomplished internally by some mcus that have on-chip real-time clocks. even so, for date, month, and leap year measurement, this task can take substantial amounts of bandwidth and code space. the ds1307 64x8 serial real-time clock provides calendar and time keeping functions along with system-enhancing non-volatile ram. with a 2-wire interface, timekeeping can be managed easily. some applications of using the ds1307 are: ? logging of chronological events ? tracking power down time of a system ? providing alarm functions f r e e s c a l e s e m i c o n d u c t o r , i f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN1759 2 the non-volatile ram (random-access memory) also gives the user additional applications such as: ? power down information storage for consumer electronics like tvs, vcrs, and hand-held portables ? identification number storage for remote addressing or security ? storage of telecommunication information like phone number recall and speed dialing this application note describes the interface between the mc68hc705j1a (j1a) and the ds1307. circuitry and example code are given to demonstrate the interface between the two parts. features the ds1307 provides these features: ? real-time clock counts seconds, minutes, hours, day of the week, date, month, and year. ? leap year compensation valid up to 2100 ? 56 bytes of non-volatile ram for data storage ? 2-wire serial interface ? programmable square wave output with frequencies of 1 hz, 4.096 khz, 8.192 khz, and 32.768 khz ? automatic power switching to battery when main power fails ? in battery backup mode, less than 500 na consumed at 25 c ? 8-pin dip or soic package ? optional industrial temperature range of C40 c to +85 c description the ds1307 is a low-power binary coded decimal (bcd) clock calendar that provides seconds, minutes, hours, day, date, month, and year. in addition, it has 56 bytes of non-volatile ram. end-of-the-month adjustments are automatic for months with less than 31 days. the device also corrects for leap years. the clock can operate in either 12-hour or 24-hour mode. in 12-hour mode, an a.m./p.m indicator is used. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note ds1307 hardware interface AN1759 3 the ds1307 has built-in power management circuitry to detect power failures on the v dd pin and when detected will switch power over to the battery back-up pin, v bat . access to the device is terminated when v dd falls below 1.25 x v bat . further accesses to the device are not allowed. on power up, the device switches power from v bat to v dd when the v dd pin is 0.2 volts above v bat . once v dd is higher than 1.25 x v bat , normal operations can continue. address and data are communicated via the 2-wire bus. the ds1307 operates as a slave at all times and is accessed by first transmitting the ds1307s identification code on the bus. ds1307 hardware interface pinout and pin descriptions figure 1. ds1307 pinout v dd and gnd these pins serve as the main power source for the device. when +5 volts is applied to this pin, the device is fully accessible and data can be read or written. if the power on the v dd pin falls below 1.25 x v dd , the device switches its power supply to v bat . at this point, reading and writing to the device is prohibited. the timekeeping function and non- volatile ram are unaffected. v bat this pin is the power input for any standard 3-volt lithium battery or other 3-volt source. for proper operation, this voltage must be held between 2.5 and 3.5 volts. a lithium battery with at least a 35-ma hours rating will back up the ds1307 for more than 10 years in the absence of power. 1 2 3 4 8 7 6 5 x2 v bat gnd x1 sqw/out scl sda v dd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN1759 4 x1 and x2 these pins are used to connect a 32.768-khz crystal to the device. no other capacitors or resistors are needed for this crystal circuit. the internal oscillator circuitry is designed for a crystal with load capacitance of 12.5 pf. for the test circuit described in this application note, an epson c-001r crystal was used. the digi-key part number for this device is se3201-nd. sqw/out when enabled, this pin outputs one of four selectable frequencies: ? 1 hz ? 4.096 khz ? 8.192 khz ? 32.768 khz the 1-hz signal can be used to feed an external interrupt pin on an mcu. this allows the mcu to use minimal bandwidth when servicing the timekeeping function of a system. when disabled, the pin acts as a normal output pin. it is controlled via the ds1307 control register. scl the scl pin is the clock input for the ds1307 2-wire serial interface. sda the sda pin is an i/o pin used to transmit and receive data off the 2-wire serial interface. sda is an open-drain pin that requires an external pullup resistor. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note ds1307 hardware interface AN1759 5 block diagram figure 2. ds1307 block diagram serial interface the ds1307 supports the bidirectional, 2-wire protocol. the protocol has these characteristics: ? any device sending out data is defined as a transmitter. ? any device receiving data is defined as a receiver. ? the device controlling the transfer is called the master. ? the device being controlled is called the slave. ? the master initiates all transactions. ? the master always provides the clock for both transmit and receive operations. ? the ds1307 is always considered the slave. ? the clock signal is called scl. ? the data signal is called sda. ? all data is sent most significant bit (msb) first. figure 3 shows the 2-wire bus interface between a master and slave. square oscillator & divider serial bus interface power control address real-time clock ram ram 56 x 8 x1 x2 v dd v bat gnd sqw/out sda scl control wave out register logic f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN1759 6 figure 3. 2-wire serial bus interface bus idle in idle mode, both the sda and scl are held high. start transfer all transfers begin with the start transfer condition. this is done by bringing the sda pin from high to low while the scl pin is high. the ds1307 is monitoring the bus for this signal and will not start any transactions until this condition is met. see figure 4 . stop transfer all transfers must be terminated with the stop transfer condition. this is done by bringing the sda pin from low to high while the scl pin is high. a stop transfer can be used only after the transmitting device releases the bus. see figure 4 . +5 v ds1307 2-wire port rx tx 5k w rx tx port pin bus master tx rx scl sda direction f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note ds1307 hardware interface AN1759 7 figure 4. start and stop transfer timing data transfer data is transmitted on the rising edge of scl. data can only be changed while scl is low. the receiving device samples the bus after scl goes high. there is one clock pulse per bit of data transmitted. see figure 5 . figure 5. data transfer timing acknowledge transfer the acknowledge transfer is a type of handshaking convention used to signify that a successful transfer of data has taken place. after the transmitting device sends out the eighth bit of a byte of data, it releases the bus. the master sends out a ninth clock signal and the receiver acknowledges the transfer by pulling sda low. once the transmitter reads the low condition of sda, it proceeds by taking over the bus and sending out the next byte of data. if the ds1307 is transmitting data and the master wants to end further transmissions, the master sends a no ack signal (high) back to the ds1307. this tells the ds1307 that no more transfers are needed and the stop transfer condition will be initiated soon. see figure 6 for these different timing patterns. scl sda start stop scl sda data change data stable data stable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN1759 8 figure 6. acknowledge timing 2-wire protocol example an example of the protocol needed to write $10 to address $07 of the ds1307 is: 1. the master transmits a start transfer. 2. the master transmits the ds1307 7-bit identification code, %1101000. 3. since this is a data write transfer, the master then transmits a 0. 4. since a byte has just been transmitted, the receiver (ds1307) will now send out a low to acknowledge the transfer. 5. the master reads the sda pin for a low. 6. the master sends out the address of $07 to the ds1307 and receives back an acknowledge. 7. the master sends out the data, $10, to the ds1307 and receives back an acknowledge. the ds1307 writes $10 to address $07. 8. finally, a stop transfer is sent to the ds1307 to complete the transaction. scl sda ack from slave scl sda ack from master if last receive, sda is high f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note ds1307 software interface AN1759 9 ds1307 software interface memory map the ds1307s memory map is shown in figure 7 . the real-time clock registers are located in address locations $00 to $07. the 56 bytes of non-volatile ram are located in address locations $08 to $3f. during multibyte addresses, the address pointer wraps around to $00 after it reaches $3f. figure 7. ds1307 memory map register map the real-time clock registers are shown in detail in figure 8 . the time and calendar are set by writing to the appropriate registers. the information is in binary coded decimal (bcd) format. to enable the processor, write a 0 to the clock halt bit in register $00. the ds1307 is shipped with this bit set to 1. either 12-hour or 24-hour clock format can be used. if bit 6 of register $02 is a 0, the device is in 24-hour mode. likewise, when bit 6 is a 1, the device is in 12-hour mode. bit 5 of address $02 is used for the second seconds minutes ram 56x8 hours day date month year control $00 $07 $08 $3f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN1759 10 10 hours when in 24-hour mode. when using 12-hour mode, bit 5 is a 1 for p.m. and a 0 for a.m. figure 8. ds1307 register map control register the control register is used to control the sqw/out pin. out controls the output level of the sqw/out pin when sqwe = 0. 1 = sqw/out pin high 0 = sqw/out pin low sqwe enables the oscillator square wave on the sqw/out pin 1 = square wave enabled 0 = square wave disabled rs square wave output frequency ? rs1 = 0 and rs0 = 0 > 1 hz ? rs1 = 0 and rs1 = 1 > 4.096 khz ? rs1 = 1 and rs1 = 0 > 8.192 khz ? rs1 = 1 and rs1 = 1 > 32.768 khz $00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 seconds minutes hours clock 10 seconds 10 minutes halt day date month year x x x x x x x x 12 24 10 hr a/p 10 hr x xx 10 date 10 month 10 year xx x x out sqwe rs1 rs0 $01 $02 $03 $04 $05 $06 $07 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note ds1307 software interface AN1759 11 data write sequence the first byte transmitted in a write to the ds1307 is its 7-bit identification code followed by the r/ w bit. for writes, this bit will be 0. the next byte transmitted is the ds1307 address pointer. after this, bytes of data to be written to the ds1307 ram are transmitted. after each byte of data is written, the address pointer is incremented. see figure 9 . figure 9. data write sequence data read sequence the first byte transmitted in a read from the ds1307 is its 7-bit identification code followed by the r/ w bit. for reads, this bit will be 1. then the ds1307 will begin transmitting data back to the master. as long as the ds1307 receives clocks and acknowledgments, it keeps transmitting data. the starting address is the previous address pointer from the last write transaction. if needed, a write sequence with only an address can be used to initialize the address pointer for reads. note: remember that for the last byte read, the master sends back a no ack to the ds1307. figure 10. data read sequence start 1101000 ds1307 address r/ w 0 ack xxxx,xxxx address pointer ack xxxx,xxxx data (n) ack xxxx,xxxx data (n+?) ack stop start 1101000 ds1307 address r/ w 1 ack xxxx,xxxx data (n) ack xxxx,xxxx data (n+?) ack stop f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN1759 12 mc68hc705j1a hardware interface with only 20 pins, the j1a is one of the smallest members of the hc05 family. it has a total of 1240 bytes of erasable programmable read-only memory (eprom) and includes 14 i/o (input/output) pins. the schematic used for testing the j1a to ds1307 interface on the mmevs development system is shown in figure 11 . the pins used to drive the ds1307 on the j1a are listed here also. ? port a, bit 0 this i/o pin (scl) is configured as an output to drive the serial clock pin, scl, of the ds1307. ? port a, bi t 1 this i/o pin (sda) is used to transmit and receive data on the sda pin of the ds1307. for further information on the hc705j1a, consult the mc68hc705j1a technical databook (mc68hc705j1a/d). figure 11. j1a-to ds1307 interface test circuit 1 2 3 4 8 7 6 5 x2 v bat gnd x1 sqw/out scl sda v dd +5 v ds1307 pa 0 pa 1 mmevs 3-v battery +5 v 4.7 k w tp +5 v 4.7 k w j1a interface epson #c-301r 32.768-khz xtal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note mc68hc705j1a software interface AN1759 13 mc68hc705j1a software interface i/o driving or manipulation is the process of toggling i/o pins with software instructions to create a certain hardware peripheral. the hc05 cpu provides special instructions specifically to manipulate single i/o pins. five subroutines were created to provide an easy application programming interface (api). these routines are: ? start_ser sends out a start condition on the bus ? stop_ser sends out a stop condition on the bus ? txd the master takes the contents of acca and transmits it msb first to the ds1307. the master also checks for acknowledgement from the ds1307. ? rxd after the master addresses the ds1307 with its identification code and the read bit, the ds1307 transmits a byte of data back to the master. this routine reads that byte and puts it into acca. the master also generates an acknowledgment back to the ds1307. ? rxd_last this routine is just like rxd but it is used for the last byte read from the ds1307. it does not generate an acknowledgment back to the ds1307. the flowcharts for the ds1620 serial i/o drivers are shown in flowcharts for the test interface . these routines were written especially for the ds1307 and may not be able to properly drive other mcu peripherals with 2-wire serial buses. a typical application would use the sqw/out pin on the ds1307. when configuring this pin for a 1-hz signal, feed the signal to the irq pin of an mcu. an interrupt routine can be created to read the contents of the ds1307 every time a 1-hz signal hits the irq pin. this should take minimal cpu bandwidth and provide the user an easy way to retrieve time and date information. the main test routine was written to verify the bus interface between the ds1307 and the j1a. it writes a known date and time into the ds1307 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN1759 14 and then reads it back out. the data read is put into a ram buffer on the hc05. when the emulator is stopped, read the contents of the hc05 ram buffer to verify the transmission process. the test routine sequence is shown in figure 15 . the assembly code for the test routine is provided in the section titled code listing . the sequence of tests is: 1. configure the device to turn on a 1-hz signal on the sqw/out pin. a. transmit a start condition. b. transmit the ds1307 code to write to the device of %11010000. c. transmit the control register address and then $10. d. transmit a stop condition. 2. write start time. a. transmit a start condition. b. transmit the ds1307 code to write to the device of %11010000. c. transmit the starting address of $00, the seconds register. d. transmit saturday, june 20, 1998, 4:30:00 p.m. (by writing a 0 to bit 7 of the seconds register, the crystal circuit has been turned on.) e. transmit a stop condition. 3. read time and date, store away to hc05 ram buffer. a. transmit a start condition. b. transmit the ds1307 code to write to the device of %11010000. c. transmit the starting address of $00. d. transmit a stop condition. e. transmit a start condition. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note development tools AN1759 15 f. transmit the ds1307 code to read from the device of %11010001. g. read the date and time and store away to hc05 ram. h. transmit a stop condition. since the real-time clock is running, you can restart the code at step 3 and verify that it is keeping time. this routine demonstrates the interface software needed to communicate with the ds1307. although the j1a was used, any hc05 device could utilize this interface code. minor adjustments of port pins and memory maps might be necessary. development tools the interface was created and tested using these development tools: ? m68mmpfb0508 freescale mmevs platform board ? x68em05j1a freescale j1a emulation module ? win ide version 1.02 editor, assembler, and debugger by p&e microcomputer systems f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN1759 16 flowcharts for the test interface figure 12. start_ser and stop_ser subroutines start_ser take sda low take scl low return from sub stop_ser take scl high take sda high return from sub f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note flowcharts for the test interface AN1759 17 figure 13. txd subroutine txd set x = 8 as a counter left shift acca, carry = msb decrement x carry = 1? yes no set sda = 1 set sda = 0 x = 0?, loop done? no yes toggle clock scl = 1 scl = 0 make sda an input scl = 1 sda pin = 0? no ack yes slave sent ack scl = 0 make sda an output a a return from sub no ack error loop f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN1759 18 figure 14. rxd/rxd_last subroutines rxd/rxd_last make sda an input scl=1 x = 0? yes, received 8-bit data no sda pin = 0? carry bit = sda yes no rotate left acca puts carry bit into acca msb scl = 0 make sda an output sda = 0 set x = 8 as a counter decrement x toggle clock scl=1 scl=0 return from sub rxd ack with sda = 0 rxd_last no ack with sda = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note flowcharts for the test interface AN1759 19 figure 15. flowchart for main test routine start config control reg transmit start_ser txd ds1307_write txd control txd $10 transmit stop_ser write start time transmit start_ser txd ds1307_write txd seconds txd start_seconds txd start_minutes txd start_hours txd start_day txd start_date txd start_month txd start_year transmit stop_ser read time, store to hc05 ram transmit start_ser txd ds1307_write txd seconds transmit ser_stop transmit start_ser txd ds1307 rxd store to buf_seconds rxd store to buf_minutes rxd store to buf_hours rxd store to buf_day rxd store to buf_date rxd store to buf_month rxd_last store to buf_year transmit ser_stop infinite loop f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN1759 20 code listing ************************************************************************************ * * file name: ds1307.asm * example code for the mc68hc705j1a interface to the * dallas ds1307 serial real time clock * ver: 1.0 * date: june 1, 1998 * author: mark glenewinkel * freescale field applications * consumer systems group * assembler: p&e ide ver 1.02 * * for code explanation and flow charts, please consult freescale application note * "add a non-volatile clock to the mc68hc705j1a" literature # AN1759/d * ************************************************************************************ *** system definitions and equates ************************************************** *** internal register definitions porta equ $00 ;porta ddra equ $04 ;data direction for porta *** application specific definitions ser_port equ $00 ;porta is ser_port scl equ 0t ;porta, bit 0, clock signal sda equ 1t ;porta, bit 1, data signal ds1307_write equ $d0 ;addresses the ds1307 for write ds1307_read equ $d1 ;addresses the ds1307 for read seconds equ $00 ;ds1307 address for seconds minutes equ $01 ;ds1307 address for minutes hours equ $02 ;ds1307 address for hours day equ $03 ;ds1307 address for the day date equ $04 ;ds1307 address for the date month equ $05 ;ds1307 address for the month year equ $06 ;ds1307 address for the year control equ $07 ;ds1307 address for control *** memory definitions eprom equ $300 ;start of eprom mem ram equ $c0 ;start of ram mem reset equ $7fe ;vector for reset *** time start definitions for test *** start on saturday, june 20th, 1998, 4:30:00 pm start_seconds equ $00 ;0 seconds start_minutes equ $30 ;30 minutes start_hours equ $64 ;4 hours, pm, 12 hour mode start_day equ $06 ;saturday start_date equ $20 ;20th start_month equ $06 ;june start_year equ $98 ;1998 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note code listing AN1759 21 *** ram variables ****************************************************************** * buffer for test reading data from the ds1307 org ram buf_seconds db 1 ;buffer on hc05 for seconds buf_minutes db 1 ;buffer on hc05 for hours buf_day db 1 ;buffer on hc05 for the day buf_date db 1 ;buffer on hc05 for the date buf_month db 1 ;buffer on hc05 for the month buf_year db 1 ;buffer on hc05 for the year *** main routine ******************************************************************* org eprom ;start at begining of eprom *** intialize ports start lda #$03 ;init ser_port sta ser_port lda #$03 ;make ser_port pins outputs sta ddra *** ds1307 configuration *** turn on osc, turn on sqw/out pin with 1 hz signal jsr start_ser ;start serial transmission lda #ds1307_write ;address the ds1307 device, write jsr txd lda #control ;send address of control reg jsr txd lda #$10 ;send config data jsr txd jsr stop_ser ;stop serial transmission *** write starting time to ds1307 jsr start_ser ;start serial transmission lda #ds1307_write ;address the ds1307 device, write jsr txd lda #seconds ;start address of ds1307 jsr txd lda #start_seconds ;write seconds jsr txd lda #start_minutes ;write minutes jsr txd lda #start_hours ;write hours jsr txd lda #start_day ;write day jsr txd lda #start_date ;write date jsr txd lda #start_month ;write month jsr txd lda #start_year ;write year jsr txd jsr stop_ser ;stop serial transmission f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN1759 22 *** read time, store away in hc05 time buffer for verification * write starting address jsr start_ser ;start serial transmission lda #ds1307_write ;address the ds1307 device, write jsr txd lda #seconds ;start address of ds1307 read jsr txd jsr stop_ser ;stop serial transmission * read time data put in hc05 buffer jsr start_ser ;start serial transmission lda #ds1307_read ;address the ds1307 device, read jsr txd jsr rxd sta buf_second ;read seconds, store to buffer jsr rxd sta buf_minutes ;read minutes, store to buffer jsr rxd sta buf_hours ;read hours, store to buffer jsr rxd sta buf_day ;read the day, store to buffer jsr rxd sta buf_date ;read the date, store to buffer jsr rxd sta buf_month ;read the month, store to buffer jsr rxd_last sta buf_year ;read the year, store to buffer jsr stop_ser ;stop serial transmission dummy bra dummy ;test sequence is over *** subroutines ******************************************************************** *** sends out start command on bus start_ser bclr sda,ser_port ;sda=0 bclr scl,ser_port ;scl=0 rts *** sends out stop command on bus stop_ser bset scl,ser_port ;scl=1 bset sda,ser_port ;sda=1 rts *** routine takes contents of acca and transmits it serially to *** the ds1307, msb first *** looks for ack, goes to error routine if no ack txd ldx #8t ;set counter write asla ;carry bit = msb bcc j1 bset sda,ser_port ;sda=1 bra clock_it ;branch to clock_it j1 bclr sda,ser_port ;sda=0 brn j1 ;evens it out f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note code listing AN1759 23 clock_it bset scl,ser_port ;scl=1 bclr scl,ser_port ;scl=0 decx ;decrement counter bne write * check for ack bclr sda,ddra ;sda is input bset scl,ser_port ;scl=1 brclr sda,ser_port,j2 ;if sda=0, slave ack ack_error bra ack_error ;no slave ack, error loop j2 bclr scl,ser_port ;scl=0 bset sda,ddra ;sda is output rts ;return from sub *** routine clocks the ds1307 to read data from sda, msb first *** 8 bit contents are put in acca *** generates ack back to slave rxd bclr sda,ddra ;make the sda pin on j1a input ldx #8t ;set counter read bset scl,ser_port ;scl=1 brclr sda,ser_port,j3 ;carry bit = sda j3 rola ;put carry bit into acca msb bclr scl,ser_port ;scl=0 decx ;decrement counter bne read * ack back to slave bset sda,ddra ;make the sda pin on j1a output bclr sda,ser_port ;sda=0 bset scl,ser_port ;scl=1 bclr scl,ser_port ;scl=0 rts ;return from sub *** routine clocks the ds1307 to read data from sda, msb first *** 8 bit contents are put in acca *** generates no ack back to slave, signals last read to ds1307 rxd_last bclr sda,ddra ;make the sda pin on j1a input ldx #8t ;set counter read_last bset scl,ser_port ;scl=1 brclr sda,ser_port,j4 ;carry bit = sda j4 rola ;put carry bit into acca msb bclr scl,ser_port ;scl=0 decx ;decrement counter bne read_last * no ack back to slave bset sda,ddra ;make the sda pin on j1a output bset sda,ser_port ;sda=1 bset scl,ser_port ;scl=1 bclr scl,ser_port ;scl=0 rts ;return from sub *** vector table ******************************************************************* org reset dw start f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required application note references mc68hc705j1a technical data , freescale document order number mc68hc705j1a/d, 1996. m68hc05 applications guide , freescale document order number m68hc05ag/ad, 1996. ds1307 datasheet , dallas semiconductor, 1997. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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